Results

  1. LSB
    1. Hardware implementation:
      1. Area utilisation
      2. Power Consumption
      3. Timing report
      4. Cycle count
        1. Ripes:
        2. C implementation:
        3. HW implementation:
  2. Source code

LSB

Hardware implementation:

Area utilisation

(Post implementation)

icon

Power Consumption

icon

Timing report

Max frequency = 333 MHz

Cycle count

Ripes:

161,219

C implementation:

1771519819

HW implementation:

7500 cycles (Verilog counter)

Source code

Github

© Shreenithi S and Hrishikesh Nair. Last modified: June 25, 2021. Website built with Franklin.jl and the Julia programming language.